Design and Production Process of CMOS Fabrication
Submitted
By
Lokanath Tripathy(115)
Satya
Swarup(89)
Sumeet
Singh(98)
Branch of Engineering: Electronics and Instrumentation
Engineering
Introduction
The
following discussion will concentrate on the well-established CMOS fabrication
technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors
be built on the same chip substrate. To accommodate both nMOS and pMOS devices,
special regions must be created in which the semiconductor type is opposite to the
substrate type. These regions are called wells or tubs. A p-well is created in
an n-type substrate or, alternatively, an n-well is created in a p-type
substrate. In the simple n-well
CMOS
fabrication technology presented here, the nMOS transistor is created in the
p-type substrate, and the pMOS transistor is created in the n-well, which is
built into the p-type substrate. In the twin-tub CMOS technology, additional tubs
of the same type as the substrate can also be created for device optimization.
The
simplified process sequence for the fabrication of CMOS integrated circuits on a
p-type silicon substrate is shown in Fig. 1.1. The process starts with the
creation of the n-well regions for pMOS transistors, by impurity implantation
into the substrate. Then, a thick oxide is grown in the regions surrounding the
nMOS and pMOS active regions. The thin gate oxide is subsequently grown on the
surface through thermal oxidation. These steps are followed by the creation of
n+ and p+ regions (source, drain, and channel-stop implants) and by final
metallization (creation of metal interconnects).
Fig.1.1 Simplified process sequence
for the fabrication of the n-well CMOS integrated circuit with a single
polysilicon layer, showing only major fabrication steps.
Fabrication Process Flow: Basic Steps
Note that
each processing step requires that certain areas are defined on chip by
appropriate masks. Consequently, the integrated circuit may be viewed as a set
of patterned layers of doped silicon, poly-silicon, metal, and insulating
silicon dioxide. In general, a layer must be patterned before the next layer of
material is applied on the chip. The process used to transfer a pattern to a layer
on the chip is called lithography. Since each layer has its own distinct
patterning requirements, the lithographic sequence must be repeated for every
layer, using a different mask. To illustrate the fabrication steps involved in
patterning silicon dioxide through optical lithography, let us first examine the
process flow shown in Fig. 1.2. The sequence starts with the thermal oxidation
of the silicon surface, by which an oxide layer of about 1 m thickness, for
example, is created on the substrate (Fig. 1.2(b)). The entire oxide surface is
then covered with a layer of photoresist, which is essentially a
light-sensitive, acid-resistant organic polymer, initially insoluble in the
developing solution (Fig.1.2(c)). If the photoresist material is exposed to ultraviolet
(UV) light, the exposed areas become soluble so that they are no longer
resistant to etching solvents. To selectively expose the photoresist, we have
to cover some of the areas on the surface with a mask during exposure. Thus,
when the structure with the mask on top is exposed to UV light, areas which are
covered by the opaque features on the mask are shielded. In the areas where the
UV light can pass through, on the other hand, the photoresist is exposed and becomes
soluble (Fig. 1.2(d)).
Fig.1.2 Process steps required for patterning of silicon
dioxide.
The type of
photoresist which is initially insoluble and becomes soluble after exposure to
UV light is called positive photoresist. The process sequence shown in Fig. 1.2
uses positive photoresist. There is another type of photoresist which is
initially soluble and becomes insoluble (hardened) after exposure to UV light,
called negative photoresist. If negative photoresist is used in the
photolithography process, the areas which are not shielded from the UV light by
the opaque mask features become insoluble, whereas the shielded areas can
subsequently be etched away by a developing solution. Negative photoresists are
more sensitive to light, but their photolithographic resolution is not as high
as that of the positive photoresists. Therefore, negative photoresists are-used
less commonly in the manufacturing of high-density integrated circuits. Following
the UV exposure step, the unexposed portions of the photoresist can be removed
by a solvent. Now, the silicon dioxide regions which are not covered by hardened
photoresist can be etched away either by using a chemical solvent (HF acid) or by
using a dry etch (plasma etch) process (Fig. 1.2(e)). Note that at the end of
this step, we obtain an oxide window that reaches down to the silicon surface
(Fig. 1.2(f)). The remaining photoresist can now be stripped from the silicon
dioxide surface by using another solvent, leaving the patterned silicon dioxide
feature on the surface as shown in Fig. 1.2(g).
The
sequence of process steps illustrated in detail in Fig. 1.2 actually
accomplishes a single pattern transfer onto the silicon dioxide surface, as
shown in Fig. 1.3. The fabrication of semiconductor devices requires several
such pattern transfers to be performed on silicon dioxide, polysilicon, and
metal. The basic patterning process used in all fabrication steps, however, is
quite similar to the one shown in Fig. 1.2. Also note that for accurate
generation of high-density patterns required in sub-micron devices, electron
beam (E-beam) lithography is used instead of optical lithography. In the following, the main processing steps involved
in the fabrication of an n-channel MOS transistor on a p-type silicon substrate
will be examined.
Fig. 1.2 Process steps required for patterning of silicon
dioxide (continued).
Fig. 1.3 The result of a single lithographic patterning sequence
on silicon dioxide, without showing the intermediate steps. Compare the un-patterned
structure (top) and the patterned structure (bottom) with Fig. 1.2(b) and Fig.
1.2(g), respectively.
Fabrication of the nMOS
Transistor
The process
starts with the oxidation of the silicon substrate (Fig. 1.4(a)), in which a relatively
thick silicon dioxide layer, also called field oxide, is created on the surface
(Fig. 1.4(b)). Then, the field oxide is selectively etched to expose the
silicon surface on which the MOS transistor will be created (Fig. 1.4(c)).
Following this step, the surface is covered with a thin, high-quality oxide
layer, which will eventually form the gate oxide of the MOS transistor (of fig
1.4(d)). On the top of thin oxide layer, a layer of polysilicon (polycrystalline
silicon) is deposited (Fig. 1.4(e)). Polysilicon is used both as gate electrode
material for MOS transistors and also as an interconnect medium in silicon
integrated circuits. Un-doped polysilicon has relatively high resistivity.
The-resistivity of polysilicon can be reduced, however, by doping it with
impurity atoms. After deposition the polysilicon layer is patterned and etched
to form the interconnection and the MOS transistor gates (Fig. 1.4(f)). The
thin gate oxide not covered by polysilicon is also etched away, which exposes
the bare silicon surface on which the source and drain junctions are to be formed
(Fig. 1.4(g)). The entire silicon surface is the n-doped with a high
concentration of impurities, either through diffusion or ion implantation (in
this case with donor atoms to produce n-type doping). Fig. 1.4(h) shows that
the doping penetrates the exposed areas on the silicon surface, ultimately
creating two n-type regions (source and drain junctions) in the p-type
substrate. The impurity doping also penetrates the polysilicon on the surface,
reducing its resistivity.
Fig. 1.4 Process flow for the fabrication of an n-type MOSFET on
p-type silicon.
Note that
the polysilicon gate, which is patterned before doping, actually defines the
precise location, of the channel region and, hence, the location of the source
and the drain regions. Since this procedure allows very precise positioning of
the two regions relative to the gate, it is also called the self-aligned
process.
Fig. 1.4 Process flow for the fabrication of an n-type MOSFET on
p-type silicon (continued).
Once the
source and drain regions are completed, the entire surface is again covered with
an insulating layer of silicon dioxide (Fig. 1.4(i)). The insulating oxide
layer is then patterned in order to provide contact windows for the drain and
source junctions (Fig. 1.4(j)). The surface is covered with evaporated aluminium
which will form the interconnection (Fig. 1.4(k)). Finally, the metal layer is
patterned and etched, completing the interconnection of the MOS transistors on
the surface (Fig. 1.4(l)). Usually, a second (and third) layer of metallic
interconnect can also be added on top of this structure by creating another
insulating oxide layer, cutting contact (via) holes, depositing, and patterning
the metal.
Device Isolation Techniques
The MOS
transistors that comprise an integrated circuit must be electrically isolated from
each other during fabrication. Isolation is required to prevent unwanted conduction
paths between the devices, to avoid creation of inversion layers outside the
channel regions of transistors, and to reduce leakage currents. To achieve a
sufficient level of electrical isolation between neighbouring transistors on a
chip surface, the devices are typically created in dedicated regions called
active areas, where each active area is surrounded by a relatively thick oxide
barrier called the field oxide. One possible technique to create isolated
active
areas on silicon surface is first to grow a thick field oxide over the entire
surface of the chip, and then to selectively etch the oxide in certain regions,
to define the active areas. This fabrication technique, called etched field-oxide
isolation, is already illustrated in Fig. 1.4(b) and Fig. 1.4(c). Here, the field
oxide is selectively etched away to expose the silicon surface on which the
MOS/h transistor will be created. Although the technique is relatively
straightforward, it also has 29 some drawbacks. The most significant disadvantage
is that the thickness of the field oxide leads to rather large oxide steps at
the boundaries between active areas and isolation Fabrication (field) regions.
When polysilicon and metal layers are
Fig. 1.4 Process flow for the fabrication of an n-type MOSFET on
p-type silicon (continued).
deposited
over such boundaries in of MOSFETs subsequent process steps, the sheer height
difference at the boundary can cause cracking of deposited layers, leading to
chip failure. To prevent this, most manufacturers prefer isolation techniques
that partially recess the field oxide into the silicon surface, resulting in a
more planar surface topology.
Local Oxidation of Silicon (LOCOS)
The local
oxidation of silicon (LOCOS) technique is based on the principle of selectively
growing the field oxide in certain regions, instead of selectively etching away
the active areas after oxide growth. Selective oxide growth is achieved by
shielding the active areas with silicon nitride (Si3N4)
during oxidation, which effectively inhibits oxide growth. The basic steps of
the LOCOS process are illustrated in Fig. 1.5. First, a thin pad oxide (also
called stress-relief oxide) is grown on the silicon surface, followed by the
deposition and patterning of a silicon nitride layer to mask (i.e., to define) the
active areas (Fig. 1.5(a)). The thin pad oxide underneath the silicon nitride
layer is used to protect the silicon surface from stress caused by nitride
during the subsequent process steps. The exposed areas of the silicon surface,
which will eventually form the isolation regions, are doped with a p-type
impurity to create the channel-stop implants that surround the transistors
(Fig. 1.5(b)). Next, a thick field oxide is grown in the areas not covered with
silicon nitride, as shown in Fig. 1.5(c). Notice that the field oxide is
partially recessed into the surface since the thermal oxidation process also
consumes some of the silicon. Also, the field oxide forms a lateral extension
under the nitride layer, called the bird's beak region. This lateral encroachment
is mainly responsible for a reduction of the active area. The silicon nitride
layer and the thin pad oxide layer are etched in the final step (Fig. 1.5(d)),
resulting in active areas surrounded by the partially recessed field oxide. The
LOCOS process is a popular technique used for achieving field oxide isolation with
a more planar surface topology. Several additional measures have also been developed
over the years to control the lateral bird's beak encroachment, since this encroachment
ultimately limits device scaling and device density in VLSI circuits.
Fig. 1.5 Basic steps of the LOCOS process to create oxide
isolation around active areas.
The CMOS n-Well Process
Having
examined the basic process steps for pattern transfer through lithography and
having gone through the fabrication procedure of a single n-type MOS
transistor, we can now return to the generalized fabrication sequence of n-well
CMOS integrated circuits, as shown in Fig. 1.1. In the following figures, some
of the important process steps involved in the fabrication of a CMOS inverter
will be shown by a top view of the lithographic masks and a cross-sectional
view of the relevant areas. The n-well CMOS process starts with a moderately
doped (with impurity concentration typically less than 1015 cm-3) p-type
silicon substrate. Then, an initial oxide layer is grown on the entire surface.
The first lithographic mask defines the n-well region. Donor atoms, usually
phosphorus, are implanted through this window in the oxide.
Layout Design Rules
The
physical mask layout of any circuit to be manufactured using a particular
process must conform to a set of geometric constraints or rules, which are
generally called layout design rules. These rules usually specify the minimum
allowable line widths for physical objects on-chip such as metal and
polysilicon interconnects or diffusion areas, minimum feature dimensions, and
minimum allowable separations between two such features. If a metal line width
is made too small, for example, it is possible for the line to break during the
fabrication process or afterwards, resulting in an open circuit. If two lines
are placed too close to each other in the layout, they may form an unwanted
short circuit by merging during or after the fabrication process. The main
objective of design rules is to achieve, for any circuit to be manufactured
with a particular process, a high overall yield and reliability while using the
smallest possible silicon area. Note that there is usually a trade-off between
higher yield, which is obtained through conservative geometries, and better
area efficiency, which is obtained through aggressive, high-density placement
of various features on the chip. The layout design rules which are specified
for a particular fabrication process normally represent a reasonable optimum
point in terms of yield and density. It must be emphasized, however, that the design
rules do not represent strict boundaries which separate "correct"
designs from "incorrect" ones. A layout which violates some of the
specified design rules may still result in an operational circuit with reasonable
yield, whereas another layout observing all specified design rules may result
in a circuit which is not functional and/or has very low yield. To summarize,
we can say, in general, that observing the layout design rules significantly
increases the probability of fabricating a successful product with high yield.
The design
rules are usually described in two ways:
i.
Micron
rules, in which the layout constraints such as minimum
feature sizes and minimum allowable feature separations are stated
in terms of absolute dimensions in micrometres, or,
ii.
Lambda
rules, which specify the layout constraints in terms of a
single parameter (λ) and thus allow linear, proportional scaling of all
geometrical constraints.
Lambda-based
layout design rules were originally devised to simplify the industry-standard
micron-based design rules and to allow scaling capability for various
processes. It must be emphasized, however, that most of the submicron CMOS
process design rules do not lend themselves to straightforward linear scaling.
The use of lambda-based design rules must therefore be handled with caution in
submicron geometries. In the following, we present a sample set of the
lambda-based layout design rules devised for the MOSIS (MOS Implementation
System) CMOS process and illustrate the implications of these rules on a
section of a simple layout which includes two transistors (Fig. 1.6). The complete
set of MOSIS CMOS scalable design rules are also illustrated in colour in Plate
6 and Plate 7.
MOSIS Layout Design Rules (sample set)
Rule number Description λ-Rule
Active area rules
R1 Minimum
active area width 3λ
R2 Minimum
active area spacing 3λ
Polysilicon
rules
R3 Minimum
poly width 2λ
R4 Minimum
poly spacing 2λ
R5 Minimum
gate extension of poly over active 2λ
R6 Minimum
poly-active edge spacing 1λ
(poly outside active area)
R7 Minimum
poly-active edge spacing 3λ
(poly inside active area)
Metal rules
R8 Minimum
metal width 3λ
R9 Minimum
metal spacing 3λ
Contact rules
R10 Poly
contact size 2λ
R11 Minimum
poly contact spacing 2λ
R12 Minimum
poly contact to poly edge spacing 1X
R13 Minimum
poly contact to metal edge spacing 1λ
R14 Minimum
poly contact to active edge spacing 3λ
R15 Active
contact size 2λ
R16 Minimum
active contact spacing 2λ
(on the same active region)
R17 Minimum
active contact to active edge spacing 1λ
R18 Minimum
active contact to metal edge spacing 1λ
R19 Minimum
active contact to poly edge spacing 3λ
R20 Minimum
active contact spacing 6λ
(on different active regions)
Fig. 1.6 Illustration of some of the typical MOSIS layout design
rules.
MOSFET Layout Design
Fig. 1.6
Illustration of some of the typical MOSIS layout design rules (continued).
